There are a number of semiconductor die packages. Low profile packages that include specific leadframe structures and specific drain clip structures are shown and described in U.S. patent application Ser. No. 10/271,654, filed Oct. 14, 2002, entitled “Thin, Thermally Enhanced Flip Chip In A Leaded Molded Package” by Rajeev Joshi and Chung-Lin Wu, which is herein incorporated by reference in its entirety for all purposes. In this patent application, a semiconductor die is mounted to a leadframe structure with solder. A drain clip is bonded to the topside of the die. The die is encapsulated with a molding material.
While such semiconductor packages are useful, improvements could be made. For example, one problem to be addressed is the problem of solder joint reliability. During the processing of the above described die package, a semiconductor die is mounted to the leadframe with solder. Solder joints are formed between the leadframe and the semiconductor die. The narrow spaces between solder joints and between the die and the leadframe need to be filled with the molding material. It is difficult to fill these narrow spaces with molding material. If the spaces are not filled with molding material, gaps can form in the semiconductor die package. The molding material may be non-uniform, and this can cause stress in the solder joints, which can cause them to fracture. Another problem to be addressed is the problem of delamination between the leadframe structure and the molding material. If the molding material and the leadframe structure do not strongly adhere to each other, they can separate from each other thus increasing the likelihood that the die package may fail over time.
Embodiments of the invention address these and other problems individually and collectively.